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TDA7513T
SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSOR
1

FEATURES
AM/FM TUNER FOR CAR-RADIO INTEGRATED TUNING PLL VARIABLE-BANDWITH FM IF FILTER (ISS) FULLY INTEGRATED FM STEREO DECODER FULLY INTEGRATED FM NOISE BLANKER HIGHLY INTEGRATED AUDIO PROCESSOR
Figure 1. Package
TQFP80

Table 1. Order Codes
Part Number TDA7513T Package TQFP80
2
DESCRIPTION
The TDA7513T is the first device for car-radio applications that combines full RF front-end functions with audio-processing capabilities. As far as FM and AM functions are concerned , the TDA7513T features front-end processing, including the digital tuning PLL, IF processing with demodulation and variable-bandwidth IF filtering (ISS), stop station and quality detection functions, FM stereo decoding by means of a fully-integrated, adjustment-free dedicated PLL and, finally, FM noise blanking. The FM stereo decoder and noise blanker functions are realized entirely without external components. The audio processor section comprises input seFigure 2. Pins Connection
FMIFAMP1OUT
lectors for two quasi-differential external sources, volume control, tone control (bass, mid and treble), balance and fading control to drive four output channels. A soft mute function and an RDS mute function are included to handle source change as well as RDS AF search without abrupt changes in the audio level. Most of the parameters in the front-end section are I2Cbus-driven and therefore under the control of the car-radio maker. The I2C bus allows furthermore the user to realize the full electric alignment of all the external coils, therefore removing the need for hand-made or mechanical adjustments.
FMIFAMP2OUT
FMIFAMPREF
AMIF2AMPIN
FMIFAMP1IN
FMIFAMP2IN
AMMIX2OUT
AMIF2AMPREF
AMAGC2TC
FMMIX2IN1
FMNAGCIN
MIX1OUT1
MIX1OUT2
FMMIX2IN2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VREF5V TUNGND AMMIX1IN1 AMMIX1IN2 AMAGC1TC AMAGC1IOUT AMAGC1VOUT FMMIX1IN1 RFGND FMMIX1IN2 FMAGCIOUT FMWAGCIN FMAGCVOUT FMANTADJ FMRFANDJ OSCGND VCOE VCOB OSCVCC LFOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MULTIPATHTC RDSMUTE AUDIOMUTE QUALITY SMETER SD SCL SDA FMMUTETC TUNEROUT TUNERIN IN1L IN1COM IN1R IN2R IN2COM IN2L ACLOUT ACLIN ACROUT
IFGND
IFVCC
TUNVCC
TUNQUALITY
DIGVCC
DIGGND
VREF3V
OUTFR
OUTRL
XTALG
DEVTC
APGND
APVCC
PLLGND
PLLVCC
OUTRR
OUTFL
XTALD
LFREF
ACRIN
ISSTC
LFIN
LFHC
FMDEMREF
SMETERTC
DEMGND
D03AU1527
June 2004
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BLOCK DIAGRAM
Figure 3. Tuner Section
FMIFAMP2OUT FMIFAMP1OUT FMIFAMPREF/ AMIF2REF FMIFAMP1IN/ AMMIX2IN FMIFAMP2IN FMMIX2IN+ FMNAGCIN SMETERTC FMMIX2INMIX1OUT+ MIX1OUTTUNGND VREF5V ISSTC DEVTC TUNQUALITY FMMUTETC TUNEROUT DEMGND FMDEMREF SD TUNVCC sfFS SMETER fFS
IF1GND
IFT1ADJ
FMAGCIOUT FMAGCVOUT FMWAGCIN FMMIX1IN+ FMMIX1INRFGND VCOB VCOE OSCVCC OSCGND
IF1VCC
FM AGC FM MIX1
fFS
AMP1
FM
AMP2
FM
FM MIX2
SMETER FILTER
SMETER SLIDER
5V REF
ufFS
ISS
VCO 10.7M DIV 4,6,8,10 AM/ FM FS METER 450K
ufFS
AdjChDet MPathDet OverDevDet QUALITY
fFS
+
AdjChDet SoftMute
fFS
AMMIX1IN+ AMMIX1IN-
AM MIX1 AM AGC1
MUTE
450K FM DEMOD AMP
AUDIO
AMAGC1IOUT AMAGC1VOUT AMAG1CTC LFREF LFIN LFHC LFOUT DIGVCC DIGGND FMANTADJ FMRFADJ
ufFS
PLL
400K 450K 10.25M AMP2
AM
IFC 10.25M AM DEM AM AGC2
fFS ufFS
SD
FM FE ADJ
PLLVCC PLLGND
XTAL OSC
XTALD
AM MIX2 IFT2ADJ
AMIF2AMPREF AMIF2AMPIN AMMIX2OUT
SDAint
I2C BUS
AMAGC2TC
SCLint ACKint
Figure 4. Stereo Decoder / Audio Processor Section
XTALG
AM/FM L TUNERIN
IN
GAIN
PILOT CANC
ROLL-OFF COMP
DEMOD ST. BLEND
HIGH CUT
AM/FM R
RDSMUTE RDSMUTE
PILOT DETECTOR PLL LEVEL ADJUST
stereo
RDSMUTE
sfFS SDA SCL
ST. BLEND/HI CUT CONTROL Level Det DevDet Noise Det Disch Time Const QUALITY DET AUTO ZERO SOFT MUTE VOL
TREBLE MID BASS
I2C BUS
SDAint SCLint ACKint
NOISE BLANKER MPATH DET
ufFS
MPATHTC
QUALITY ACLOUT ACLIN
IN1L IN1COM IN1R IN2L IN2COM IN2R AM/FM L
IN
GAIN
SPKR SPKR SPKR SPKR mute
OUTRL OUTFL
IN
GAIN
AUTO ZERO
OUTFR OUTRR ACRIN ACROUT
AM/FM R
3V REF
VREF3V APGND AUDIOMUTE APVCC
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Table 2. Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN NAME VREF5V TUNGND AMMIX1IN1 AMMIX1IN2 AMAGC1TC AMAGC1IOUT AMAGC1VOUT FMMIX1IN1 RFGND FMMIX1IN2 FMAGCIOUT FMWAGCIN FMAGCVOUT FMANTADJ FMRFANDJ OSCGND VCOE VCOB OSCVCC LFOUT LFREF LFIN LFHC PLLVCC PLLGND XTALG XTALD DIGVCC DIGGND TUNQUALITY ISSTC DEVTC VREF3V APGND APVCC OUTRR OUTRL OUTFR OUTFL ACRIN 5V reference tuner general ground am mix1 input am mix1 input am agc1 filter capacitor am agc1 current output am agc1 voltage output fm mix1 input rf ground fm mix1 input fm agc current output fm agc RF input fm agc voltage output fm antenna filter adjustment fm rf filter adjustment vco ground am/fm vco emitter am/fm vco base vco supply (8V) PLL loop filter output PLL loop filter reference PLL loop filter input PLL loop filter high-current input PLL back-end supply PLL back-end ground ref osc gate ref osc drain digital dirty supply (8V) digital ground tuner combined output of multipath and adjacent channel detectors ISS time constant deviation detector time constant 3V reference audio processor/stereo decoder ground audio processor/stereo decoder supply (8V) audio out audio out audio out audio out ac coupling right input PIN FUNCTION
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Table 2. Pin Description (continued)
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN NAME ACROUT ACLIN ACLOUT IN2L IN2COM IN2R IN1R IN1COM IN1L TUNERIN TUNEROUT FMMUTETC SDA SCL SD SMETER QUALITY AUDIOMUTE RDSMUTE MULTIPATHTC FMDEMREF DEMGND SMETERTC AMIF2AMPREF AMIF2AMPIN AMAGC2TC AMMIX2OUT FMMIX2IN2 FMMIX2IN1 FMIFAMP2OUT FMIFAMP2IN TUNVCC FMIFAMPREF FMIFAMP1OUT FMIFAMP1IN FMNAGCIN IFGND MIX1OUT2 MIX1OUT1 IFVCC ac coupling right output ac coupling left input ac coupling left output audio in2 left audio in2 common audio in2 right audio in1 right audio in1 common audio in1 left am audio/fm mpx input am audio/fm mpx output fm muting time constant capacitor I2C bus data I2C bus clock am/fm station detector output am/fm smeter output quality output audio mute control rds mute control multipath detector time constant fm demodulator reference capacitor fm demodulator ground am/fm smeter filtering capacitor am if2 amp feedback capacitor am if2 amp input am agc2 filter capacitor am mix2 single-ended output fm mix2 input fm mix2 input fm if1 amp2 output fm if1 amp2 input tuner general supply (8V) fm if1 amps reference capacitor fm if1 amp1 output fm if1 amp1 input fm agc IF input if1 ground am/fm mix1 output am/fm mix1 output if1 supply (8V) PIN FUNCTION
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ELECTRICAL CHARACTERISTCS
4.1 FM (VCC = 8V; Tamb = 25C; Vsg = 60dBV; fc = 98.1MHz; fdev = 40kHz; fmod = 1kHz unless otherwise specified) Table 3. General (audioprocessor all flat and stereo decoder input gain = 4dB )
Symbol US SNR LS THD Vout ISN IFCS Icc Parameter Useable sensitivity Signal to Noise ratio Limiting Sensitivity Total Harmonic Distortion Audio output level Interstation noise IF Counter sensitivity DC current OSCVcc PLLVcc DIGVcc TUNVcc IF1Vcc APVcc Soft Mute OFF; @ Vout = -3dB fdev = 40kHz fdev = 75kHz rms Vout @ RF OFF; Soft Mute OFF Test Condition SNR = 40dB Min Typ 0 66 -4 0.1 0.15 375 -13 2 5.7 1.9 9.8 50 13.4 27.3 10 0.3 0.5 Max Unit dBV dB dBV % % mV dB dBV mA mA mA mA mA mA
Table 4. Mixer1
Symbol Gv IIP3 CIFT1 Parameter conversion gain 3rd order intercept point IFT1 adjustment capacitor min max step Rin input resistance (single ended) FMMIX1IN+ and FMMIX1IN- w.r.t. gnd Test Condition from RFT secondary to IFT1 secondary loaded with 330 referred to RFT secondary Between MIXOUT+ and MIXOUT0 8.25 0.55 10 Min Typ 9 Max Unit dB dBV pF pF pF
Table 5. Front-end Adjustment (VRFadj and VANTadj referred to VLFOUT)
Symbol Vantadj min max step VRFadj min max step Parameter Test Condition Min Typ -40 40 1.29 -40 40 1.29 Max Unit % % % % % %
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Table 6. AGC (wide AGC input connected to RFT primary through 10pF and 1K)
Symbol WAGCsp WAGCRin NAGCsp KNAGCsp Parameter Wide AGC starting point FMWAGCIN input resistance Narrow AGC starting point (max sensitivity) Keyed narrow AGC starting point (min sensitivity) FMNAGCIN input resistance Smeter for Keyed narrow AGC maximum sensitivity Smeter for Keyed narrow AGC minimum sensitivity min max Vout min max AGCVRout FMAGCVOUT output resistance minimum programming maximum programming minimum programming maximum programming AGC OFF AGC ON AGC ON AGC OFF Vcc0.5 100 8 0.1 0.5 V(SMETERTC) @ narrow AGC starting point = KNAGCsp V(SMETERTC) @ narrow AGC starting point = NAGCsp VRFTprimary @ I(FMAGCOUT) = 5A; Keyed AGC OFF VRFTprimary @ I(FMAGCOUT) = 5A; Keyed AGC ON; V(SMETERTC)<0.9V Test Condition VRFTprimary @ I(FMAGCOUT) = 5A Min Typ 84 125 95 109 Max Unit dBV dBV dBV
NAGCRin KAGCTH high
10 0.9 2.5 1.6 3.2 0.1
K V V V V A mA V V K
KAGCTH low
Iout
Table 7. IF Amplifier 1 (Input at FMIFAMP1IN, fc = 10.7MHz, no mod) (Output at FMIFAMP1OUT loaded with 330) (antenna level = FMIFAMP1IN - 31dB)
Symbol G IIP3 Rin Rout Gain 3rd order intercept point input resistance (single-ended) output resistance referred to FMIFAMP1IN FMIFAMP1IN w.r.t. gnd Parameter Test Condition Min Typ 18 126 330 330 Max Unit dB dBV
Table 8. IF Amplifier 2 (Input at FMIFAMP2IN, fc = 10.7MHz, no mod) (Output at FMIFAMP2OUT loaded with 330) (antenna level = FMIFAMP2IN - 45dB) Gain MUST BE SET to 14dB for ISS operation.
Symbol G Parameter minimum gain Test Condition programmable gain Min Typ 6 8 10 maximum gain IIP3 Input 3rd order intercept point referred to FMIFAMP2IN, G = 8dB 14 134 Max Unit dB dB dB dB dBV
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Symbol Rin Rout Parameter input resistance (single-ended) output resistance Test Condition FMIFAMP2IN to gnd Min Typ 330 330 Max Unit
Table 9. Field-strength Meter (Input at FMMIX2IN; fc = 10.7MHz, no mod) (antenna level = V67 - 49dB)
Symbol FS1 FS2 FS3 FSR FFSS FSmeter1 FSmeter2 FSmeter3 FSmeter filtering resistor Filtered FSmeter Slider min max step Parameter Test Condition V(FMMIX2IN+) = 50 dBV V(FMMIX2IN+) = 70 dBV V(FMMIX2IN+) = 90 dBV SMETERTC pin Min Typ 1.4 2.7 4.4 10.7 0 1.5 50 Max Unit dBV dBV dBV k V V mV
Table 10. MPX output (output at TUNEROUT)
Symbol Gc Vaudio Parameter conversion gain audio level peak, 40kHz deviation Test Condition Min Typ 5.42 217 Max Unit mV/kHz mVp
Table 11. Field-strength Stop Station (Input at FMMIX2IN - fc = 10.7MHz, no mod) (antenna level = V69 - 49dB)
Symbol FSSSmin FSSSmax FSSSstep Parameter minimum threshold maximum threshold threshold step Test Condition Vthr = 0.4V Vthr = 3.4V Vthr = 200mV Min Typ 50 78 3 Max Unit dBV dBV dB
Table 12. Soft Mute
Symbol SMD Parameter Soft Mute Depth min Test Condition Min Typ 13.4 16 19.5 max MCVlow MCVhigh ACMcl Mute control voltage low Mute control voltage high Adjacent channel mute clamp voltage min max step V(FMMUTETC) @ No mute attenuation V(FMMUTETC) @ Max mute attenuation Max V(FMMUTETC) in Adjacent Channel conditions 24 0.2 2 500 2000 100 Max Unit dB dB dB dB V V mV mV mV
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Table 13. ISS Filter (FMIF1AMP1 gain MUST be set to 14dB) *
Symbol BW1 BW2 BWwb Parameter Wide bandwidth Narrow bandwidth Weather Band bandwidth Test Condition Full bandwidth @ -3dB Min Typ 120 80 30 Max Unit kHz kHz kHz
* if ISS function is not used, SEEK must be set to "ON" in FM
AM (VCC = 8V; Tamb =25C; Vsg = 74dBV,emf; fc = 999kHz; 30% modulation; fmod = 400Hz unless otherwise specified). Table 14. General (with 20pF/65pF dummy antenna; input levels @ SG,emf; output @ audioprocessor output; audioprocessor all flat; stereo decoder input gain = 5.75dB)
Symbol US SNR MS THD Parameter Useable sensitivity Signal to Noise ratio Maximum Sensitivity Total Harmonic Distortion @ Vout = -10dB mod =30%, Vsg = 74dBV mod =80%, Vsg = 74dBV mod =30%, Vsg = 120dBV mod =80%, Vsg = 120dBV THDLF Vout ISN IFCS Icc THD @ low frequency Audio output level Interstation noise level IF Counter sensitivity DC current OSCVcc PLLVcc DIGVcc TUNVcc IF1Vcc APVcc mod =30%, Vsg = 74dBV, fmod=100Hz rms Vout @ RF OFF 8 Test Condition SNR = 20dB Min Typ 26 56 20 0.59 1.48 1.88 3 2 266 -35 10 5.6 1.9 12.1 68 7.8 27 -31 20 60 Max Unit dBV dB dBV % % % % % mV dB dBV mA mA mA mA mA mA
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Table 15. Mixer1 (Input at AMMIX1IN+, no mod)
Symbol Gv IIP3 Rin CIFT1 Parameter conversion gain Input 3rd order intercept point input resistance (differential) IFT1 adjustment capacitor min max step Test Condition from AMMIX1IN+to IFT1 secondary loaded with 330 referred to AMMIX1IN+ AMMIX1IN+ w.r.t. AMMIX1INBetween MIXOUT+ and MIXOUTMin Typ 13 130 1.2 0 8.25 0.55 Max Unit dB dBV k pF pF pF
Table 16. AGC1 (Wide AGC input = AM Mixer1 input; Narrow AGC input = AM Mixer2 input; Ultra Narrow AGC input = AM IF2 Amp input; fWAGCin = 999kHz, fNAGCIN = 10.7MHz, fUNAGCin = 450kHz)
Symbol WAGCsp Wide AGC starting point NAGCsp NarrowAGC starting point UNAGCsp Ultra Narrow AGC starting point AGC1R Iout Vout AGC1VRout min max min max AMAGC1VOUT output resistance Parameter min max min max min max AMAGC1TC pin AGC OFF AGC ON AGC ON AGC OFF 3.38 23 0.4 0.5 AMMIX1IN+ @ I(AMAGC1VOUT) = 1 uA AMMIX1IN+ @ I(AMAGC1VOUT) = 1 uA Test Condition AMMIX1IN+ @ I(AMAGC1VOUT) = 1 uA Min Typ 85 104 79 97 50 97 100 1 Max Unit dBV dBV dBV dBV dBV dBV K A mA V V K
AGC1 filtering resistor
Table 17. Mixer2 (Input at AMMIX2IN, fc = 10.7MHz, no mod)
Symbol Gv, max Gv, min IIP3 Rin CIFT2 Parameter conversion gain, no AGC conversion gain, full AGC Input 3rd order intercept point input resistance IFT2 adjustment capacitor min max step Test Condition from AMMIX2IN to IFT2 secondary loaded with 2k from AMMIX2IN to IFT2 secondary loaded with 2k referred to AMMIX2IN, no AGC AMMIX2IN w.r.t. ground Between AMMIX2OUT and gnd Min Typ 15 -7 120 330 0 24 1.6 Max Unit dB dB dBV pF pF pF
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Table 18. IF2 amplifier (Input at AMIF2AMPIN, fc = 450kHz, no mod)
Symbol Gv, max Parameter gain, no AGC max prog Test Condition Min Typ 64.8 62.8 61.7 60.2 58.3 55.8 min prog Gv Rin gain decrease in full AGC input resistance w.r.t. Gv, max AMMIX2IN w.r.t. ground 53.2 -40 2 dB k Max Unit dB
Table 19. AGC2
Symbol AGC2R Parameter AGC2 filtering resistor reception seek Test Condition Min Typ 150 5 Max Unit k k
Table 20. Audio output (output at TUNEROUT, 2.7k load)
Symbol Vaudio audio level Parameter Test Condition rms, 30% modulation Min Typ 305 Max Unit mV
Table 21. Field-strength Meter (Input at AMIF2AMPIN; fc = 450 kHz, no mod) (SG,emf level = V65 - 29dB)
Symbol FS1 FS2 FS3 FSR FSmeter1 FSmeter2 FSmeter3 FSmeter filter resistor Filtered FSmeter Slider min max FFSS min max step Parameter Test Condition V(AMIF2AMPIN) = 50 dBV V(AMIF2AMPIN) = 70 dBV V(AMIF2AMPIN) = 90 dBV SMETERTC pin Min Typ 0.7 2.1 4.2 16.5 75 0 1.5 48.4 Max Unit dBV dBV dBV k k V V mV
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4.2 OSCILLATORS (VCC = 8V; Tamb =25C) Table 22. VCO
Symbol Vvco C/N Parameter Oscillation level Carrier to Noise ratio Test Condition Tuning Voltage = 4V f = 1kHz Min 106 85 Typ Max 108 Unit dBV dBc/Hz
Table 23. XTAL
Symbol Vxtal FXTAL Parameter Oscillation level Adjustment min frequency range max step Test Condition @ XTAL gate referred to 10.25 MHz centered condition Min Typ 131 -4 +4 238 Max Unit dBV kHz kHz Hz
Table 24. Audio Processor (VS = 8V; Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
Symbol INPUT GAIN GIN MIN GIN MAX GSTEP Rin CMRR Min. Input Gain Max. Input Gain Step Resolution Input Resistance Common Mode Rejection Ratio Any input pin to gnd VCM = 1VRMS @ 1kHz VCM = 1VRMS @ 10kHz VOLUME CONTROL GMAX ASTEP EA ET VDC Max Gain Step Resolution Attenuation Set Error Tracking Error DC Steps Adjacent Attenuation Steps From 0dB to GMIN SOFT MUTE/AFS AMUTE TD Mute Attenuation Delay Time T1 T2 T3 T4 VTH low Low Threshold for SM-/AFS- Pin 1 80 100 0.48 0.96 20.2 40.4 1 dB ms ms ms ms V G = -20 to 20dB G = -60 to 20dB 13 0.5 -1.25 -4 15 1 0 0 17 1.5 1.25 3 2 dB dB dB dB dB mV mV -1 13 0.5 70 45 45 0 15 1 100 70 60 1 17 1.5 130 dB dB dB k dB dB Parameter Test Condition Min. Typ. Max. Unit
QUASI DIFFERENTIAL STEREO INPUT 1&2
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Table 24. Audio Processor (continued) (VS = 8V; Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
Symbol VTH high CRANGE ASTEP fC BASS CONTROL Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 QBASS Quality Factor Q1 Q2 Q3 Q4 DCGAIN Bass-Dc-Gain DC = off DC = on MID CONTROL CRANGE ASTEP fC Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 QBASS Quality Factor Q1 Q2 TREBLE CONTROL CRANGE ASTEP fC Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 SPEAKER ATTENUATORS RIN GMAX AMAX ASTEP AMUTE EE VDC Input Impedance Max Gain Max Attenuation Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Adjacent Attenuation Steps 17.5 13 -70 0.5 80 25 15 -79 1 90 2 1.5 32.5 17 k dB dB dB dB dB mV 13 0.5 8 10 12 14 15 1 10 12.5 15 17.5 17 1.5 12 15 18 21 dB dB kHz kHz kHz kHz 13 0.5 450 0.9 1.35 1.8 0.9 1.8 15 1 500 1 1.5 2 1 2 17 1.5 550 1.1 1.65 2.2 1.1 2.2 dB dB Hz kHz kHz kHz 13 0.5 54 63 72 90 0.9 1.1 1.3 1.8 -1 3.5 15 1 60 70 80 100 (150)2 1 1.25 1.5 2 0 4.4 17 1.5 66 77 88 110 1.1 1.4 1.7 2.2 1 5.5 dB dB dB dB Hz Hz Hz Hz Parameter High Threshold for SM-/AFS-Pin Test Condition Min. 4 Typ. Max. Unit V
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Table 24. Audio Processor (continued) (VS = 8V; Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
AUDIO OUTPUTS Symbol VCLIP RL CL ROUT VDC GENERAL Gqd Gstd eNO Gain (QDin) Gain (Tuner) Output Noise (QDin) Quasi-differential Input Tuner Input (STD InGain=4dB) BW = 20 Hz to 20 kHz output muted; all flat BW = 20 Hz to 20 kHz all gain = 0dB S/N Signal to Noise Ratio (QDin) all gain = 0dB flat; VO = 2VRMS bass treble at 12dB; A-weighted; VO = 2.6VRMS d Distortion (QDin) VIN = 1VRMS; all stages 0dB VIN = 1VRMS; Bass & Treble = 12dB SC ET Channel separation Left/Right (QDin) Total Tracking Error AV = 0 to -20dB AV = -20 to -60dB BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 2.5 -5 5 0.4 0.8 V V A V 80 -1 -2 0 0 1 2 20 100 96 0.012 0.05 0.1 0.1 0.5 7.5 15 dB dB V V dB dB % % dB dB dB Parameter Clipping Level Output Load Resistance Output Load Capacitance Output Impedance DC Voltage Level 30 3.9 Test Condition THD = 0.3% Min. 2.2 2 10 120 Typ. 2.6 Max. Unit VRMS k nF V
1) The SM pin is active low (Mute = 0) 2) See note in Programming Part
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4.3 STEREO DECODER. Table 25. Stereo Decoder (Vcc = 8V; deemphasis time constant = 50s, VMPX = 305mVrms (75kHz deviation), fm= 1kHz, Gv = 4dB, Tamb = 27C; unless otherwise specified)
Symbol Rin GV Parameter Input Resistance Stereo decoder input gain FM AM min Test Condition Min. 70 1.4 Typ. 100 2 0.5 2.25 4.0 max SVRR a THD (S+N)/N Supply Voltage Ripple Rejection Max. channel Separation Total Harmonic Distortion Signal plus Noise to Noise Ratio A-weighted, S = 2Vrms @ APout for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Mono, PTH = 0 -6 min max step @TUNERIN Bit 7, Subadr, 10 = 0, VLEVEL >> VHCH Bit 7, Subadr, 10 = 1, VLEVEL >> VHCH Bit 7, Subadr, 10 = 0, VLEVEL >> VHCL Bit 7, Subadr, 10 = 1, VLEVEL >> VHCL 276 25 50 100 150 50 75 150 225 75 100 200 300 VCO Vtuning fixed to reference voltage 328 619 9.4 80 Vripple = 100mV; f = 1KHz 35 30 5.75 60 45 0.02 91 0.3 Max. 130 2.6 Unit k k dB dB dB dB dB dB % dB
MONO/STEREO-SWITCH VPTHST1 VPTHST0 VPTHMO1 VPTHMOO PLL f/f f0 Lock Range Center frequency range +6 % kHz kHz kHz mV s s s s Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage 15 25 12 19 mV mV mV mV
PILmax
Maximum input pilot voltage Deemphasis Time Constant Deemphasis Time Constant Highcut Time Constant Highcut Time Constant
DEEMPHASIS and HIGHCUT
HC50 HC75 HC50 HC75
STEREOBLEND- and HIGHCUT-CONTROL REF5V LGmin LGmax LGstep VSBLmin VSBLmax VSBLstep VHCHmin VHCHmax VHCHstep Internal Reference Voltage Min. LEVEL Gain Max. LEVEL Gain LEVEL Gain Step Resolution Min. Voltage for Mono Max. Voltage for Mono Step Resolution Min. Voltage for NO Highcut Max. Voltage for NO Highcut Step Resolution 4.7 -1 8 0.3 25 54 2.2 38 62 5 5 0 10 0.67 29 58 4.2 42 66 8.4 5.3 1 12 1 33 62 6.2 46 70 12 V dB dB dB %REF5V %REF5V %REF5V %REF5V %REF5V %REF5V
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Table 25. Stereo Decoder (continued) (Vcc = 8V; deemphasis time constant = 50s, VMPX = 305mVrms (75kHz deviation), fm= 1kHz, Gv = 4dB, Tamb = 27C; unless otherwise specified)
Symbol VHCLmin VHCLmax VHCLstep 19 38 57 76 Parameter Min. Voltage for FULL Highcut Max. Voltage for FULL Highcut Step Resolution Pilot Signal f = 19KHz Subcarrier f = 38KHz Subcarrier f = 57KHz Subcarrier f = 76KHz Test Condition Min. 12 28 2.2 40 Typ. 17 33 4.2 50 75 62 90 Max. 22 38 6.2 Unit %VHCH %VHCH %VHCH dB dB dB dB
Carrier and harmonic suppression at the output
4.4 NOISE BLANKER Table 26. Noise Blanker
Symbol VTR Parameter Trigger Threshold 0) 1) Test Condition meas. with VPEAK = 0.9V NBT = 111 NBT = 110 NBT = 101 NBT = 100 NBT = 011 NBT = 010 NBT = 001 NBT = 000 VTRNOISE Noise Controlled Trigger threshold 2) meas. with VPEAK = 1.5V NCT = 00 NCT = 01 NCT = 10 NCT = 11 VRECT Rectifier Voltage VMPX = 0mV VMPX = 50mV; f = 150KHz VMPX = 200mV; f = 150KHz VRECT DEV deviation dependent rectifier Voltage 3) meas. with VMPX = 800mV (75KHz dev.) OVD = 11 OVD = 10 OVD = 01 OVD = 00 NRD 6) = 00 Min. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 0.5 1.5 2.2 0.5 0.9 1.7 2.5 0.5 0.9 1.7 2.1 Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 2.5 0.9 1.2 2 2.8 0.9 1.4 1.9 2.4 38 32 25.5 22 Max. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 1.3 2.1 2.9 1.3 1.5 2.3 3.1 1.3 1.5 2.3 3.1 Unit mV mV mV mV mV mV mV mV mV mV mV mV V V V V V V V V V V V s s s s
VRECT FS Fieldstrength Controlled Rectifier Voltage 4)
Rectifier Voltage 4) VMPX = 0mV VLEVEL << VSBL (fully mono) Signal HOLDN in Testmode
FSC = 11 FSC = 10 FSC = 01 FSC = 00
TS
Suppression Pulse Duration 5)
BLT = 00 BLT = 10 BLT = 01 BLT = 00
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Table 26. Noise Blanker (continued)
Symbol Parameter Test Condition NRD = 00 6) NRD = 01 6) NRD = 10 6) NRD = 11 6) SRPEAK Noise Rectifier Charge Signal PEAK in Testmode Signal PEAK in Testmode PCH = 0 7) PCH = 1 7) MPNB = 00 8) MPNB = 00 8) MPNB = 00 8) MPNB = 00 8) Min. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) Typ. 0.3 0.8 1.3 2 10 20 0.3 0.5 0.7 0.9 Max. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) Unit V/ms V/ms V/ms V/ms mV/s mV/s V/ms V/ms V/ms V/ms
VRECTADJ Noise Rectifier Signal PEAK in discharge adjustment 6) Testmode
VADJMP
Noise Rectifier adjustment through Multipath 8)
(c) = by design/characterization functionally guaranteed through dedicated test mode structure (0) = All Thresholds are measured using a pulse with TR =2ms,THIGH = 2ms and TF = 10ms. The repetition rate must not icrease the PEAK voltage. 1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold 2) NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment 3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector 4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control 5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment 6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment 7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment 8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D7 for the noise rectifier multipath adjustment
4.5 MULTIPATH AND QUALITY DETECTORS Table 27. Multipath And Quality Detectors
Symbol fCMP GBPMP Parameter Center Frequency of MultipathBandpass Bandpass Gain Test Condition Stereodecoder locked on Pilottone bits D2, D1 configuration byte = 00 bits D2, D1 configuration byte = 10 bits D2, D1 configuration byte = 01 bits D2, D1 configuration byte = 11 GRECTMP Rectifier Gain bits D7, D6 configuration byte = 00 bits D7, D6 configuration byte = 01 bits D7, D6 configuration byte = 10 bits D7, D6 configuration byte = 11 ICHMP Rectifier Charge Current bit D5 configuration byte = 0 bit D5 configuration byte = 1 IDISMP Rectifier Discharge Current 0.5 Min. Typ. 19 6 12 16 18 7.6 4.6 0 off 0.5 1 1 1.5 A A mA Max. Unit kHz dB dB dB dB dB dB dB
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Table 27. Multipath And Quality Detectors
Symbol A Parameter Multipath Influence Factor Test Condition Addr. 12 / Bit 5+6 00 01 10 11 B Noise Influence Factor Addr. 16 / Bit 1+2 00 01 10 11 Min. Typ. 0.7 0.85 1 1.15 15 12 9 6 Max. Unit dB dB dB dB dB dB dB dB
5
FUNCTIONAL DESCRIPTION
5.1 FM Section 5.1.1 Mixer1, AGC and 1st IF Mixer1 is a wide dynamic range stage with low noise and large input signal performance. The mixer1 tank center frequency can be adjusted by software (IF1T). The AGC operates on different sensitivities and bandwidths (FMAGC) in order to improve the input sensitivity and dynamic range (keyed AGC). The output signals of AGC are controlled voltage and current for preamplifier and prestage P-I-N diode attenuator (see Figure 5). Two 10.7MHz amplifiers (IFG1 - fixed gain - and IFG2 - programmable) correct the IF ceramic insertion loss. 5.1.2 Mixer2, Limiter and Demodulator In this 2nd mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multi-stage limiter generates signals for the complete integrated demodulator without external tank. MPX output DC offset compensation is possible via software. 5.1.3 Quality Detection and ISS (see Figure 3) Fieldstrength Parallel to the mixer2 input a 10.7MHz limiter generates a signal for the digital IF counter and a fieldstrength output signal. This internal unfiltered fieldstrength is used for adjacent channel and multipath detection. The behaviour of this output signal can be corrected for DC offset (SL). The internally generated unfiltered fieldstrength is filtered at pin #SMETERTC and used for softmute function, FM AGC keying and generation of ISS filter switching signal for weak input level (sm). 5.1.4 Adjacent Channel Detector The input of the adjacent channel detector is AC coupled to the internal unfiltered fieldstrength. A programmable and configurable highpass or bandpass filter (ACF) and amplifier (ACG) followed by a rectifier measure the adjacent channel content. This voltage is compared with an adjustable threshold (ACWTH, ACNTH) comparator (comparator1). The output signal of this comparator generates a DC level at PIN15 with a programmable time constant. Time constant control (TISS) for the adjacent channel is made by linearly charging and discharging an external capacitor following. The charge current is fixed and the discharge current is controlled by I2C bus. This level produces digital signals (ac, ac+) after comparing by the following comparator4. The adjacent channel information after filtering and rectification is available as analog output on pin #TUNQUALITY (the gain can be selected via I2C bus) in combination with multipath content information. It is possible to enable adjacent channel content information output only via I2C bus control.
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5.1.5 Multipath Detector The input of the multipath detector is AC coupled to the internal unfiltered fieldstrength. A programmable band-pass filter (MPF) and amplifier (MPG) followed by a rectifier measures the multipath content. This voltage is compared with an adjustable threshold (MPTH) comparator (comparator2). The output signal of this comparator2 is used to disable the adjacent channel detector control of the ISS filter in case of strong multipath, which would otherwise result in bandwidth reduction because of the multipath-induced high-frequency content of the fieldstrength signal. The multipath detector influence on the adjacent channel detector is selectable by I2C bus (MPOFF). The multipath information after filtering and rectification is available as analog output on pin #TUNQUALITY (the gain can be selected via I2C bus) in combination with the adjacent channel content information. It is possible to enable multipath content information output only via I2C bus control. 5.1.6 450kHz IF Narrow Bandpass Filter (ISS filter) The device features an additional automatically selectable IF narrow bandpass filter for suppression noise and adjacent channel signals. This narrow filter has three switchable bandwidth positions: narrow range (80kHz), mid range (120kHz) and weather band (30kHz). WHen the ISS filter is not inserted the IF bandwidth (wide range) is defined only by the ceramic filter chain. The filter is switched in after mixer2 before the 450kHz limiter stage. The centre frequency can be finely adjusted (AISS) by software. 5.1.7 Deviation Detector In order to avoid excessive audio distortion the narrow ISS filter is switched OFF when overdeviation of the incoming signal is detected. The demodulator output signal is low-pass filtered and rectified to generate a DC level in an external capacitor through a software-controlled current (TDEV). This level is compared with a programmable threshold (DWTH, DTH) comparator (comparator3) to generate two digital signals (dev, dev+). 5.1.8 ISS Switch Logic All digital signals coming from adjacent channel detector, deviation detector and softmute are combined in a decision matrix to generate the control signals for the ISS filter switch. The IF bandpass switch mode can be also controlled by software (ISSON, ISS30, ISS80, ISSCTL). The switch-on of the IF bandpass can be further controlled from the outside by manipulation of the voltage at pin #ISSTC. Two application modes are available (APPM). The conditions are described in table 1. 5.1.9 Soft Mute Control The external fieldstrength signal at pin #SMETERTC is the reference for MPX mute control. The start point and mute depth are programmable over a wide range. The time constant is defined by the external capacitor connected to pin #FMMUTETC. Additionally adjacent channel mute function is supported. A software-configurable highpass / bandpass filter centered at about 100kHz followed by an amplifier and a peak rectifier generates adjacent noise information starting from the MPX output; the information is acted upon with the same time constant as the softmute by the MPX muting circuit. The adjacent channel mute starting point, slope and depth are I2C bus programmable. 5.1.10Station Detector and Seek Stop A station detection function is provided for easy seek stop operation. The unfiltered fieldstrength signal is compared with a programmable threshold and the result (logic '1' if the current station strength is higher than the threshold) is combined by an AND gate with the IF counter output (logic '1' if the current channel is centered within a programmable window around the desired frequency). The result is available on pin #SD for direct connection to the microprocessor. Channel quality assessment for RDS Alternate Frequency operation makes use of the SD signal in conjunction with analog information on adjacent channel and multipath content on pin #TUNQUALITY and channel noise (furtherly combined with multipath content information) on pin #QUALITY.
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5.2 AM Section The upconversion mixer1 is combined with a gain control circuit 1 sensing three input signals: ultra-narrow band information (from the IF2 amplifier input - pin #AMIF2AMPIN), narrow-band information (from the mixer2 input - pin #AMMIX2IN) and wide band information (from the mixer1 input - pins #AMMIX1IN+ and #AMMIX1IN-). This gain control circuit generates two output signals: a current for P-I-N diode attenuation and a voltage for the external preamplifier cascode upper base. It is possible to put in a separate narrow bandpass filter before mixer2 at PIN 58. The intervention point for first AGC on all three bands is programmable by software. The oscillator frequency for mixer1 is generated by dividing the FM VCO frequency (AMD) by 6, 8 and 10 (6 for Japan applications, 8 for Eastern European applications, 10 for Western European and North American operation). In mixer2 the IF1 is downconverted into the 450kHz IF2. The gain of mixer2 is reduced by the 2nd AGC after the gain of the subsequent IF2 amplifier has been reduced by 30dB. The mixer2 tank center frequency is software-adjustable (IF2T). After channel selection is done by the ceramic filter, a 450kHz amplifier with a gain control is included. The gain is controlled by the AGC2 loop over a 30dB range; the full gain with no AGC applied is programmable. The AM demodulation is made by multiplication of the IF2 amplifier output by the amplified and limited signal coming from the IF2 amplifier input, thus making the demodulation process inherently linear. The demodulated audio signal is low-passed by the capacitor at pin #AMAGC2TC to produce the DC AGC2 voltage. The low-pass time constant is switchable by a ratio of 30 in order to reduce the settling time of the AGC2 in 'seek' mode (AMSEEK). The FM 450kHz limiter is used to generate the square wave needed by the AM demodulator, a fieldstrength indication and to feed the AM IF counter. The fieldstrength information is generated mainly from the narrow-band signal at the input of the IF2 amplifier; since the dynamic range at that input is limited by the AGC2 action, a fieldstrength extension is made adding the contribution of the signal at the input of mixer2. Since the bandwidth there is very large, though, the latter contribution is enabled only if the strength of the narrow-band signal is higher than an internally defined threshold. The fieldstrength signal must be low-passed to remove audio content and this is done by use of the capacitor at pin #SMETERTC with an I2C bus programmable internal resistor. The value of the capacitor is determined for correct FM operation; the value of the internal resistor for AM is selectable in order to make the AM time constant suitable for AM operation. A station detection function is provided for easy seek stop operation. The fieldstrength signal is compared with a programmable threshold and the result (logic '1' if the current station strength is higher than the threshold) is combined by an AND gate with the IF counter output (logic '1' if the current channel is centered within a programmable window around the desired frequency). The result is available on pin #SD for direct connection to the microprocessor. 5.3 PLL and IF Counter Section The IC contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required to build a complete PLL system for FM and AM upconversion. For auto search stop operation an IF counter system is available. 5.3.1 PLL Frequency Synthesizer Block The counter works in a two stages configuration. The first stage is a swallow counter with a two-modulus (32/33) precounter. The second stage is an 11-bit programmable counter. The circuit receives the scaling factors for the programmable counters and the values of the reference frequency via I2C bus. The reference frequency is generated by an adjustable internal (XTAL) oscillator followed by the reference divider. The reference and step-frequencies are independently selectable (RC, PC). The phase-frequency detector outputs switches the programmable current source. The loop filter integrates the latter to a DC voltage. The current source values is programmable with 6 bits received via I2C bus (A, B, CURRH, LPF). To minimize the noise induced by the digital part of the system, a special guard area is implemented. The loop gain can be adjusted for different conditions by setting the current values of the chargepump generator.
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5.3.2 Frequency Generation for Phase Comparison The VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a 5-bit divider (A). A 5-bit register (PC0 to PC4) controls this divider. The output of the prescaler is connected to an 11bit divider (B), controlled by an 11-bit PC register (PC5 to PC15). The following expressions relate the divider output frequency (fSYN, forced by the loop to equal the reference frequency at the phase comparator input fREF) to the VCO frequency (fVCO) and to the crystal oscillator frequency (fXTAL): fXTAL = (R+1) x fREF fVCO = [33 x A + (B + 1 - A) x 32] x fREF fVCO = (32 x B + A + 32) x fREF Important: For correct operation: A 32; B A 5.3.3 Three State Phase Comparator The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator. 5.3.4 Charge Pump Current Generator This system generates correction current pulses with a polarity and a duration dictated by the phase error signal. The current absolute values are programmable through register A for high current and register B for low current. The charge pump operates in high current mode when the phase difference between between fSYN and fREF is high. The switch back to low current mode can be done either automatically as a function of the inlock detector output (setting bit LDENA to "1") or via software. After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay multiple of 1/fREF, the chargepump is forced in low current mode. A new PLL divider programming by I2C bus will switch the chargepump into high current mode. A few programmable phase errors (D0, D1) are available for inlock detection. The count of detected inlock informations to release the inlock signal is adjustable (D2, D3), to avoid switching to low current during a frequency jump. 5.3.5 Low Noise CMOS Op-amp An internal voltage divider at pin #LFREF is connected to the positive input of the low noise op-amp. The charge pump output is connected to the negative input. This internal amplifier in cooperation with external components provides the active loop filter. Only one loop filter connection is provided because the same reference frequency is used for both AM and FM operation. The pin #LFHC is connected in such a way as to partially shunt the loop filter in order to decrease the time constant of the filter itself during jumps with high current mode activated. 5.3.6 IF Counter Block The input signal for FM and AM has the same structure although FM IF is measured at IF1 (10.7MHz) and AM IF is measured at IF2 (450kHz). The degree of integration is adjustable to up to eight different measuring cycle times. The tolerance of the accepted count value is adjustable to reach the optimum compromise between search speed and evaluation precision. T center frequency of the measured count value is adjustable to fit the IF-filter tolerance. 5.3.7 The IF-Counter Mode The IF counter works in 2 modes controlled by the IFCM register. 5.3.8 Sampling Timer A 14-bit programmable (IRC) sampling timer generates the gate signal for the main counter. In FM mode a 6.25kHz frequency reference is generated for this purpose, whereas in AM mode this reference becomes 1kHz. These reference frequencies are further divided to generate the measurement time windows
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(160us - 320s ... 20.48ms for FM, 1ms - 2ms ... 128ms for AM). 5.3.9 Intermediate Frequency Main Counter This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to allow the adjustment to the peak of the IF-filter response. The counter length is automatically adjusted to the chosen sampling time and counter mode (FM, AM). The IF counter is also used to automatically perform the stereo decoder 456kHz VCO frequency adjustment. At the start the counter will be loaded with a value equivalent to the expected number of zero-crossing in the sampling time window (tSample x fIF ). If the correct frequency is applied to the IF counter input, at the end of the sampling time the main counter will have either a 0h state or a 1FFFFFh state stored. A deviation from the expected IF will result in a difference of the counter final state from either of these values. The counter final state is then compared to either 0h or 1FFFFFh minus a number of LSB's determined by the acceptable frequency window programming (EW). If the comparison result is good the IF counter output changes from LOW to HIGH and is made available outside at the pin #SD (after a NAND operation with the signal strength evaluation circuit). The following relationships apply: tTIM = (IRC + 1) / fOSC tCNT = (CF + 1697) / fIF tCNT = (CF + 448) / fIF where tTIM = IF timer cycle time (sampling time) tCNT = IF counter cycle time Counting succesful: tCNT - tERR = tTIM = tCNT + tERR Count failed: tTIM > tCNT + tERR tTIM < tCNT - tERR where tERR = discrimination window (controlled by the EW registers) The IF counter can be started only by inlock information from the PLL, and it is enabled by software (IFENA). 5.3.10Adjustment of the Measurement Time and Frequency window The measurement precision is adjustable by controlling the width of the frequency discrimination window through control registers EW0 to EW2. The center frequency of the discrimination window is adjustable by the control register CF0 to CF4. The measurement time per cycle is adjustable by setting the registers (FM mode) (AM mode)
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IFS0 - IFS2. 5.4 AUDIO PROCESSOR 5.4.1 Input Multiplexer CD quasi differential 1 CD quasi differential 2 Stereodecoder input (for both FM and AM signals). 5.4.2 Input stages The quasi-differential input stages (see figure 4) have been designed to cope with some CD players in the market having a significant high source impedance which affects strongly the common-mode rejection of "normal" differential input stages. The additional buffer of the CD input avoids this drawback and offers the full common-mode rejection even with those CD players. The quasi-differential input can also be used with normal stereo single-ended output signal sources such as TAPEOUT. 5.4.3 AutoZero In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that in theory any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid this undesired situation a special offset cancellation stage called AutoZero is implemented. This stage is located before the Volume block to eliminate all offsets generated by the Stereodecoder, the Input Stage and the In-Gain stage (please note that externally generated offsets, e.g. those generated because of leakage current into the coupling capacitors, are not cancelled). The auto-zeroing is started every time the APSD data byte 0 is selected and takes a maximum time of 0.6ms. The rationale behind this choice is that the APSD byte encodes the signal source selection, and auto-zero ought to be performed every time a new source is selected. To avoid audible clicks the audioprocessor is muted before the volume stage during this time. 5.4.4 AutoZero Remain In some cases, for example if the uP is executing a refresh cycle of the I2C bus programming, it is not necessary to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the device can be switched in the "AutoZero Remain mode" (Bit 6 of the APSD subaddress byte). If this bit is set to high, the APSD data byte 0 can be loaded without invoking the AutoZero and the old adjustment value remains. 5.4.5 Softmute The digitally controlled softmute stage allows signal muting and unmuting with a I2C bus programmable slope. The mute process can either be activated by pin #AUDIOMUTE or I2C bus. The slope is realized in a special S-shaped curve so as to slowly mute in the critical regions (see figure 5). For timing purposes the Bit 3 of the I2C bus output register is set to 1 from the start of muting until the end of unmuting. 5.4.6 BASS There are four parameters programmable in the bass filter stage: (see figs 6, 7, 8, 9): 5.4.7 Attenuation Figure 6 shows the attenuation as a function of frequency at a center frequency at a center frequency of 80Hz. 5.4.8 Center Frequency Figure 7 shows the four possible center frequencies: 60,70,80 and 100Hz. 5.4.9 Quality Factors Figure 8 shows the four possible quality factors: 1, 1.25, 1.5 and 2.
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5.4.10DC Mode In this mode the DC gain is increased by 5.1dB. In addition the programmed center frequency and quality factor is decreased by 25%: this can be used to realize different center frequencies or quality factors with respect to the values listed in the "BASS" section. 5.4.11MID There are 3 parameters programmable in the mid filter stage (see figs. 10, 11 & 12): 5.4.12Attenuation Figure 10 shows the attenuation as a function of frequency at a center frequency of 1kHz. 5.4.13Center Frequency Figure 11 shows the four possible center frequencies: 500Hz, 1kHz, 1.5kHz and 2kHz. 5.4.14Quality Factor Figure 12 shows the two possible quality factors (1 and 2) at a center frequency of 1kHz. 5.4.15TREBLE There are two parameters programmable in the treble filter stage (see figs 13, 14): 5.4.16Attenuation Figure 13 shows the attenuation as a function of frequency at a center frequency of 17.5kHz. 5.4.17Center Frequency Figure 14 shows the four possible Center Fre-quencies: 10, 12.5, 15 and 17.5kHz. 5.4.18AC Coupling In some applications additional signal manipulations are desired such as surround-sound processing or more extensive band equalizing. For this purpose a AC-Coupling is placed before the Speaker-attenuators, which can be activated or internally shorted by Bit7 in the APSD data byte 0. The input impedance of the AC Inputs is 25k. The external AC coupling is advised for those applications where very low-level "pop" performance is a must. 5.4.19Speaker Attenuator The speaker attenuators have exactly the same structure and range as the Volume stage. 5.5 STEREODECODER The stereodecoder part of the present device (see Fig. 15) contains all functions necessary to demodulate the MPX signal such as pilot tone-dependent MONO/STEREO switch as well as "stereoblend" and "highcut" functions. Stereodecoder Mute The device has a fast and easy-to-control RDS mute function meant for "freezing" the stereo decoder status during the RDS AF check time period. When this function is invoked three effects take place: *1 the stereo decoder input impedance changes to infinity (condition known as high-ohmic input); this prevents the decoupling capacitor between the pins #TUNER_OUT (tuner output) and #TUNER_IN (stereo decoder input) to be discharged by a channel with a potentially different DC output for the duration of the AF check; *2 the stereo decoder PLL pilot detector is held at the current value; *3 the external capacitor of the multipath detector used inside the stereo decoder for quality control is disconnected from the dection circuit in order to make quality checking the AF faster.
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The RDS mute is activated from pin #RDSMUTE in AND with Bit 0 of APSD data byte 9. 5.5.1 Stereo Decoder Input stage, Ingain + Infilter The stereo decoder is crossed by both the FM and the AM signal: the input impedance of the pin #TUNER_IN is different between the two modes in order to allow the same external coupling components between #TUNER_OUT and #TUNER_IN to realize different filtering functions. Whilst the input impedence in FM is 100k , in AM the input impedance is decreased to 2k: this allows the realization of typical high-pass filters with a corner frequency of 70Hz for AM and less than 5Hz for FM. The low-pass section of the typical AM transfer function is realized by use of the internal FM High-Cut filter. The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4th order input filter has a corner frequency of 80kHz and is used to attenuate spikes and nose and acts as an anti aliasing filter for the following switch capacitor filters. 5.5.2 Demodulator In the demodulator block the left and the right channel are separated from the MPX signal. In this stage the 19 kHz pilot tone is cancelled. To reach a good channel separation the device offers an I2C bus programmable roll-off adjustment which is able to finely compensate for the low-pass behaviour of the tuner section. An adjustment to better than 40dB channel separation is possible. The bits for this adjustment are located ogether with the fieldstrength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the carradio where the channel separation in relation to the fieldstrength control are trimmed. The setup of the Stereoblend characteristics, which is programmable in a wide range, is de-scribed in 2.8. 5.5.3 De-emphasis and Highcut. One filter is provided to realize de-emphasis and High-Cut filtering. The lowpass filter for the de-emphasis allows to choose between a time constant of 50s and 75s. The filter time constant can further be controlled in both cases over the range = 2 DEEMPH. The control is automatically performed as a function of the filtered field strength level: inside the highcut control range (between VHCH and VHCL) the level is converted into a 5 bit word which drives the lowpass time constant. The FM highcut function can be switched off by I2C bus (bit 0,of APSD data byte 11). The setup of the highcut characteristics is described in 2.9. In AM the high-cut filter can be programmed (bit 3 to 7 of APSD data byte 16) to a fixed value (inside the above-mentioned programmable range) in order to provide the desired lowpass characteristic of the AM signal. 5.5.4 PLL and Pilot Tone Detector The PLL is tasked with locking on the 19kHz pilot tone during a stereo transmission to allow the correct demodulation. The detector enables the stereo demodulation if the pilot tone reaches the selected pilot tone threshold VPTHST. Two different thresholds are available. The detector output can be checked by reading the status byte of the TDA7407 via I2C bus. 5.5.5 Fieldstrength Control The filtered field strength signal is fed to the stereo decoder where it can be finely adjusted and normalized so that it can be used to control the highcut and stereoblend functions. Furthermore the adjusted signal can also be used to control the noise-blanker thresholds. The unfiltered field strength meter, on the other hand, is used as input for the stereo decoder multipath detector. These additional functions are described in sections 3.3 and 4. 5.5.6 LEVEL Input and Gain To help suppress undesired high frequency modulation of the highcut and stereoblend functions the tuner filtered field strength signal (LEVEL) is lowpassed by a combination of a 1st order RC low-pass at 53kHz (working as anti-aliasing filter) and a 1st-order switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to finely adapt the LEVEL signal internally against tuner
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spread (see Testmode section 5 LEVELINTERN). The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB). 5.5.7 Stereoblend Control The stereoblend control block converts the internal LEVEL voltage (LEVELINTERN) into a demodulatorcompatible analog signal which is used to control the channel separation between 0dB and the maximum separation. This control range has a fixed upper limit which is the in-ternal reference voltage REF5V. The lower limit can be programmed between 29.2% and 58% of REF5V in 4.167% steps (see figs. 14, 15). To adjust the LEVEL voltage to the proper range two values must be defined: the LEVEL gain LG and VSBL (see fig. 15). To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain:
REF5V L G = ---------------------------------------------------------------------------------------------Fieldstrengthvoltage [ STEREO ]
The gain LG can be programmed with 4 bits. The MONO voltage VMO (0dB channel separation) can be chosen selecting VSBL. All the necessary internal reference voltages like REF5V are derived from a bandgap circuit, therefore they have a temperature coefficient which is practically zero. 5.5.8 Highcut Control The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of VHCH (see fig. 19). 5.6 NOISE-BLANKER In the automotive environment the MPX signal is disturbed by spikes produced for example by the ignition and by the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of these spikes. To perform this function the output of the stereodecoder is held at the curent voltage for a time between 22 and 38s (programmable). The block diagram of the noiseblanker is shown in fig.20. In the first stage the spikes are detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger desensitization control is implemented. Behind the trigger stage a pulse former generates the "blanking" pulse 5.6.1 Trigger Path The incoming MPX signal is highpassed by a filter with a corner frequency of 140kHz, amplified and rectified. The rectified signal (RECT) is lowpassed to generate the signal PEAK. Also noise at a frequency higher than 140kHz increases PEAK. The lowpass output voltage can be adjusted by changing the noise rectifier discharge current. The PEAK voltage is fed to a threshold generator which adds to the PEAK voltage a constant voltage VTH, thus producing the trigger threshold PEAK+VTH. Both RECT and PEAK+VTH are fed to a comparator which trig-gers a re-triggerable monoflop. The monoflop output activates the sample-and-hold circuits in the signalpath for a selectable duration. 5.6.2 Automatic Noise Controlled Threshold Adjustment (ATC) There are mainly two independent possibilities to program the trigger threshold: a programming the so-called "low threshold" in 8 steps; b programming the so-called "noise-adjusted threshold" in 4 steps The "low threshold" is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operating mode is high. If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular mechanism ("noiseadjusted threshold") is programmable in 4 steps.
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5.7 AUTOMATIC THRESHOLD CONTROL MECHANISM 5.7.1 Automatic Threshold Control by the Stereoblend Voltage Besides the noise-controlled threshold adjustment there is an additional possibility to influence the trigger threshold which depends on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed. In some cases the behavior of the noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off. 5.7.2 Over Deviation Detector If the system is tuned to stations with a high de-viation the noiseblanker might be erroneously triggered on the higher frequencies of the modulation. To avoid this unnecessary muting of the signal, the noiseblanker offers a deviation-dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. This is used to increase the PEAK voltage. The circuit offset, gain (and enabling) are programmable in 3 steps. 5.8 MULTIPATH DETECTOR Using the stereo decoder multipath detector the audible effects of a multipath condition can be minimized. A multipath condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal. An external capacitor is used to define the attack and decay times (see block diagram fig. 21). The pin #MULTIPATHTC is externally connected to a capacitor of about 47nF and the MPIN signal is internally connected to the unfiltered field strength. To avoid losing the information stored in the external capacitor during AF checks but at the same time to allow some fast multipath detection capability during the same AF check period, the external capacitor is disconnected by the MP-Hold switch. This switch is controlled directly by the pin #RDSMUTE. Moreover, selecting the "internal influence" in the configuration byte, the channel separation is automatically reduced during a multipath condition according to the voltage appearing at the pin #MULTIPATHTC. 5.8.1 Programming To obtain a good multipath performance an adaptation is necessary. Therefore tha gain of the 19kHz bandpass is programmable in four steps as well as the rectifier gain. The attack and decay times can be set by properly choosing the value of the external capacitor. 5.9 QUALITY DETECTOR The device offers a quality detector output voltage representing the quality of the FM reception conditions. This voltage is derived from MPX noise information and multipath information according to the following formula: Quality = 1.6 (Vnoise -0.8V)+ a (REF5V- VMPOUT) The noise signal is the PEAK signal of the noise blanker without additional influences. The multipath information weight "a" can be programmed between 0.7 and 1.15. The circuit output pin #QUALITY is a low impedance output able to drive external circuitry as well as suitable to be simply fed to an A/D converter for RDS applications. 5.9.1 AF Search Control The device is supplied with several functionality to support AF-checks using the stereodecoder. As already mentioned before the high ohmic mute feature at the stereo decoder input avoids any clicks during the jump condition. It is possible at the same time to evaluate the noise- and multipath-content of the alternate frequency by
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using the Quality detector output. During this time the multipath detector is automatically switched to a small time constant. One dedicated pin (#RDSMUTE) is provided in order to separate the audioprocessor-mute and stereodecoder AF-functions. 5.10 I2C-Bus Interface I2C bus protocol is supported. This protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and device being controlled is the slave. The master will always initiate data transfer and provide the clock to transmit or receive operations. The present device always acts as slave, both in transmission and in reception mode. 5.10.1Data Transition Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL is HIGH will be interpreted as START or STOP condition. 5.10.2Start Condition A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level. This "START" condition must precede any command and initiate a data transfer onto the bus. The device continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this condition has not been met. 5.10.3Stop Condition A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH level. This condition terminates the communication between the devices and forces the bus interface of the device into the initial condition. 5.10.4Acknowledge Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it received the eight bits of data. 5.10.5Data Transfer During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for proper device operation the SDA line must be stable during the SCL LOW to HIGH transition. 5.10.6Device Addressing To start the communication between two devices, the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device. The device recognizes the following two addresses: 1100010d 1000110d tuner part address stereo decoder / audio processor address (APSD)
The last bit of the start instruction defines the type of operation to be performed: - when set to "1", a read operation is selected (data are transferred from the device to the master) - when set to "0", a write operation is selected (data are transferred from the master to the device) The device connected to the bus will compare its own hardwired addresses with the slave address being transmitted after detecting a START condition. After this comparison, the device will generate an "acknowledge" on the SDA line and will perform either a read or a write operation according to the state of the R/W bit.
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5.10.7Write Operation Following a START condition the master sends a slave address word with the R/W bit set to "0". The device will generate an "acknowledge" after this first transmission and will wait for a second word (the subaddress field). This 8-bit address field provides an access to any of the 64 internal addresses (32 corresponding to the tuner address and 32 corresponding to the stereo decoder / audio processor address). Upon receipt of the subaddress the device will respond with an "acknowledge". At this time, all the following words transmitted to the device will be considered as Data. The internal address may be automatically incremented if the auto-increment mode is selected (bit S5 of the subaddress word) . After each word has been received the device will answer with an "acknowledge". 5.10.8Read Operation IF the master sends a slave address word with the R/W bit set to "1", the device will transmit one 8-bit data word. This data word content changes according to the address corresponding to the tuner or to the stereo decoder / audio processor. The information are the following: - tuner bit0: bit1: bit2: bit3: bit4: bit5: bit6: bit7: ISS filter, 1 = ON, 0 = OFF ISS filter bandwidth, 1 = 80kHz, 0 = 120kHz MPOUT,1 = multipath present, 0 = no multipath 1 = PLL is locked in , 0 = PLL is locked out fieldstrength indicator, 1 = lower as softmute threshold, 0 = higher as softmute threshold adjacent channel indicator, 1 = adjacent channel present, 0 = no adjacent channel deviation indicator, 1 = strong overdeviation present, 0 = no strong overdeviation deviation indicator, 1 = overdeviation present, 0 = no overdeviation
- stereo decoder / audio processor bit2: bit3: Soft Mute status, 1 = ON, 0 = OFF Stereo mode, 1 = stereo, 0 = mono
Table 28. ISS Modes MODE 1
sm 0 0 0 1 1 1 ac 0 1 1 X 0 1 ac+ 0 X X X 0 X dev 0 0 1 0 1 1 dev+ 0 0 X 0 X X ISSon 0 1 1 1 0 1 80KHz 0 1 0 1 0 0
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MODE 2
sm 0 0 0 0 1 1 1 1 ac 0 1 1 1 X 0 1 1 ac+ 0 0 1 0 X 0 0 1 dev 0 0 X 1 0 1 1 1 dev+ 0 0 X X 0 X X X ISSon 0 1 1 1 1 0 1 1 80KHz 0 0 1 0 1 0 0 1
Figure 5. Softmute Timing
1
Figure 7. Bass center @Gain = 14dB, Q = 1
15.0 12.5
EXT. MUTE
10.0
+SIGNAL
7.5
REF
5.0
-SIGNAL
2.5
1
2 I C BUS OUT
0.0
D97AU634
Time
10.0
100.0
1.0K
10.0K
Figure 6. Bass Control @ Fc = 80Hz, Q = 1
15.0
Figure 8. Bass Quality factors @ Gain = 14dB, fc = 80Hz
15.0 12.5
10.0
5.0
10.0
0.0
7.5
-5.0
5.0
2.5
-10.0
0.0
-15.0 10.0
100.0
1.0K
10.0K
10.0
100.0
1.0K
10.0K
Figure 9. Bass normal and DC Mode@ Gain =
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14dB, fc = 80Hz
15.0
Figure 12. Mid Q factor@ fc=1KHz,Gain =14dB
15.0
12.5
12.5
10.0
10.0
7.5
5.0
7. 5 5. 0 2. 5 0. 0 10.0 100. 0 1.0K 10.0K
2.5
0.0 10.0 100.0 1.0K 10.0K
Figure 10. Mid Control @ fc = 1KHz, Q = 1
15.0
Figure 13. Treble Control @ fc = 17.5KHz
15.0
10.0
5. 0 0. 0 5.0 -10.0
10.0
5.0
0.0
-5.0
-15.0 10.0 100. 0 1.0K 10.0K
-10.0
-15.0
Figure 11. Mid Center Frequency@ Gain =14dB, Q = 1
15.0
10.0
100.0
1.0K
10.0K
Figure 14. Treble Center Frequencies@ Gain = 14dB
15.0
12.5
10.0
12.5
7. 5 5. 0 2. 5 0. 0 10.0 100. 0 1.0K 10.0K
10.0
7.5
5.0
2.5
0.0 10.0 100.0 1.0K 10.0K
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Figure 15. Block Diagram of the Stereodecoder
Figure 16. Signal During Stereodecoder's Softmute
SOFTMUTE COMMAND t STD MUTE
t
VO
D97AU638
t
Figure 17. Internal stereobland Characteristics
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Figure 18. Relationship between unadjusted (LEVEL) and adjusted (LEVELITERN) filtered field strength signals
INTERNAL VOLTAGES REF 5V SETUP OF VST LEVEL INTERN REF 5V INTERNAL VOLTAGES SETUP OF VMO LEVEL INTERN
LEVEL VSBL VSBL
58% 29%
VMO
VST
t FIELDSTRENGHT VOLTAGE
modAU639
VMO
VST
t FIELDSTRENGHT VOLTAGE
Figure 19. Highcut Characteristics
LOWPASS TIME CONSTANT
3*Deemp
Deemp
VHCL
D97AU640
VHCH
FIELDSTRENGHT
Figure 20.
MPX RECTIFIER RECT + VTH THRESHOLD GENERATOR
MONOFLOP
HOLDN
+
PEAK LOWPASS MPOUT CONTROL +
ADDITIONAL THRESHOLD CONTROL
modAU856
Figure 21. Block diagram of the Multipath Detector
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6
SOFTWARE SPECIFICATIONS
6.1 ADDRESS ORGANIZATION (TUNER SECTION)
MSB Subaddr.
0 1 2 3 4 5 6 FM ISS DD FM audio amp. mute disable thr depth @ weak FS SEEK AM prescaler AM stop station tSAMPLE counter LSB IFC AM/FM counter MSB AMIF2amp 12 AMUNAGC FM demod noise blanker AM Smeter extens FM demodulator fine adjust test ACmute
LSB D6
Current select
Function
Charge Pump Control and STBY
D7
STBY Lock detenable
D5
D4
D3
D2
D1
D0
Low current Phase difference threshold counter LSB counter MSB counter LSB counter MSB
High current AM/FM
activation delay
fref VCOadj PLL Lock Detector,FM mode and BYPASS clockenab tests PLL Counter 1 (LSB) PLL Counter 2 (MSB) PLL Reference Counter 2 (LSB) PLL Reference Counter 2 (MSB) FM Antenna Adjustment and FM Mute Depth FM RF Adjustment, AM prescaler and Seek f IF Counter Control 1 and AM S.S. Threshold IF Counter Control 2 (central frequency and sampling time) IF Counter Reference (LSB) IF Counter Reference (MSB) and IF Counter Mode Select AM Ultra Narrow AGC Thresh., FM SMut AM IF2 Amplifier Gain, FM enable SoftMute Enable and AC test FM demodulator Adjust, FM demod noise blanker and MPtest
FM antenna adjustment
7 8 9 10 11
FM RF adjustment IFC enable tCENTER
13
MPQUAL test
14 15 16 17 18 19 20 21 22 23
ISS AC narrowband threshold ISS MP defeat AC 0
ISS AC wideband threshold ISS MP threshold ISS DD narrow/wide threshold
ISS AC gain test Smet unfiltered
ISS AC HP/BP ISS MP center
Quality Detection Adjacent ISS 30KHz on Channel ISS MP Quality Detection Multipath ctrl on Quality Detection Deviation Quality ISS Filter
ISS mode ISS DD off threshold
ISS DD time constant ISS 80/ 120 ISS on test PLL man SET 456 FM soft mute AdjChan mute gain FMSmslider IFT1 adjust man ENIFC ISS enable
ISS center SO mode Manual/ auto
ISS time constant ISS MP gain VCO adj start
PLL test, 456KHz VCO adiustment start (auto mode) 456KHz VCO adjustment (manual mode) FM Stop Station and soft Mute Thresholds Adjacent mute gain, clamping threshold and test FM Smeter slider and AM Smeter filter Time Constant
IFT1 adjust
Manual VCO frequency FM stop station
AC QUAL test
AdjChan mute clamp
AM Smeter filter TC IFT2 adjust
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MSB Subaddr.
24 25 26 27 28 29 30 ISS filter test Smeter pin test AdjChan mute disable AdjChan mute BP/HP @low FS Turner quality AdjChan gain Turner quality multipath gain
LSB D6 D5
Clksep AMWAGC AMNAGC test ISS test ISS MP/AC test TURNER AdiChan mute threshold Test ISS
D7
D4
D3
D2
XTAL adjustment
D1
D0
Function XTAL adjustment and FM IF Amp2
AM WAGC an FM MAGC keying AM NAGC an FMdemod ref frequency divider
FMIFamp2
FMNAGCkey FM demod ref frequency divider
ISS testing ISS testing Tuner and Smeter test
AdjChan mute disable, filtering and threshold
31
FS ISS activation
Tuner Quality AdjChannel and Multipath gain, FS ISS Activation
ADDRESS
MSB D7 1 D6 1 D5 0 D4 0 D3 0 D2 1 D1 0 LSB D0 R/W
SUBADDRESS
MSB S7 X S6 X S5 autoincr S4 S3 S2 subaddress S1 LSB S0
READ MODE: ISS OUTPUTS
MSB S7 DEV+ S6 DEV S5 AC S4 FS S3 INLOCK S2 MP S1 BW LSB S0 ON
6.2 SUBADDRESS ORGANIZATION (TUNER SECTION)
MSB D7 D6 D5 D4 D3 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 D2 0 0 0 0 1 D1 0 0 1 1 1 LSB D0 0 1 0 1 1 FUNCTION CHARGE PUMP High current = 0mA High current = 0.5mA High current = 1mA High current = 1.5mA High current = 7.5mA Low current = 0A Low current = 50A Low current = 100A Low current = 150A Select low current Select high current TURNER STAND-BY Turner StandBy OFF Turner StandBy ON
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SUBADDRESS 1: PLL Lock detector, FM mode and test
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 FUNCTION CHARGE PUMP VCO adjust lock Disable VCO adjust lock Enable fref BYPASS Disable fref BYPASS Enable TURNER/PLL AM/FM MODE Select AM mode Select FM mode LOCK DETECTOR CONTROL PD phase difference threshold 10ns PD phase difference threshold 20ns PD phase difference threshold 30ns PD phase difference threshold 40ns Not valid Activation delay 4x1/fREF Activation delay 6x1/fREF Activation delay 8x1/fREF Lock detector doesn't control charge pump Lock detector controls charge pump
SUBADDRESS 2: PLL Counter 1 (LSB)
MSB D7 0 0 0 1 1 1 1 D6 0 0 0 1 1 1 1 D5 0 0 0 1 1 1 1 D4 0 0 0 1 1 1 1 D3 0 0 0 1 1 1 1 D2 0 0 0 1 1 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 0 0 1 0 1 LSB = 0 LSB = 1 LSB = 2 LSB = 252 LSB = 253 LSB = 254 LSB = 255 FUNCTION
SUBADDRESS 3: PLL Counter 2 (MSB)
MSB D7 0 0 0 1 1 1 1 D6 0 0 0 1 1 1 1 D5 0 0 0 1 1 1 1 D4 0 0 0 1 1 1 1 D3 0 0 0 1 1 1 1 D2 0 0 0 1 1 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 0 0 1 0 1 MSB = 0 MSB = 256 MSB = 512 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 FUNCTION
Note: 1 Swallow mode:fVCO/fSYN = LSB + MSB + 32
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SUBADDRESS 4: Reference Counter 1 (LSB)
MSB D7 0 0 0 1 1 1 1 D6 0 0 0 1 1 1 1 D5 0 0 0 1 1 1 1 D4 0 0 0 1 1 1 1 D3 0 0 0 1 1 1 1 D2 0 0 0 1 1 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 0 0 1 0 1 LSB = 0 LSB = 1 LSB = 2 LSB = 252 LSB = 253 LSB = 254 LSB = 255 FUNCTION
SUBADDRESS 5: Reference Counter 2 (MSB)
MSB D7 0 0 0 1 1 1 1 D6 0 0 0 1 1 1 1 D5 0 0 0 1 1 1 1 D4 0 0 0 1 1 1 1 D3 0 0 0 1 1 1 1 D2 0 0 0 1 1 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 0 0 1 0 1 MSB = 0 MSB = 256 MSB = 512 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 FUNCTION
Note: 1 fVCO/fSYN = LSB + MSB + 1
SUBADDRESS 6: FM Antenna Adjustment and FM Mute Depth
MSB D7 D6 D5 D4 0 0 0 0 1 1 1 1 D3 1 1 0 0 0 0 1 1 D2 1 1 0 0 0 0 1 1 D1 1 1 0 0 0 0 1 1 LSB D0 1 0 1 0 0 1 0 1 FUNCTION FM antenna adj (proportional to Vtuning) -30% -28% -2% -0% +0% +2% +28% +30% FM Soft Mute Depth 25dB 20dB 16dB 13.5dB ISS deviation detector disabling threshold relative to weak fild ISS activation threshold (byte 31 bit 3-00 -100mV +100mV
-
-
-
-
-
-
0 1 0 1
0 0 1 1
0 1
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SUBADDRESS 7: FM RF Adjustment AM Prescaler and Seek
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FM RF adj (proportional to Vtuning) 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 -30% -28% -2% -0% +0% +2% +28% +30% AM VCO divider ratio 0 0 1 1 0 1 0 1 10 8 6 4 SEEK MODE 0 1 Seek OFF Seek ON FUNCTION
SUBADDRESS 8 : IF Counter Control 1 and AM S.S. Threshold
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 IF COUNTER CONTROL 0 1 0 1 0 1 0 1 Not valid Not valid Not valid f = 6.25kHz (FM) 1kHz (AM UPC) f = 12.5kHz (FM) 2kHz (AM UPC) f = 25kHz (FM) 4kHz (AM UPC) f = 50kHz (FM) 8kHz (AM UPC) f = 100kHz (FM) 16kHz (AM UPC) IF counter disable/stand by IF counter enable AM Stop Station Threshold 0mV 150mV 2100mV 2250mV FUNCTION
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SUBADDRESS 9: If Counter Control 2
MSB D7 D6 D5 D4 0 0 0 0 0 0 0 0 1 1 1 D3 0 0 1 1 1 1 1 1 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 LSB D0 0 1 0 1 0 1 0 1 0 1 1 FUNCTION FM antenna adj (proportional to Vtuning) fcenter = 10.60625MHz (FM) 449KHz (AM) fcenter = 10.61250MHz (FM) 450KHz (AM) fcenter = 10.66875MHz (FM) 459KHz (AM) fcenter = 10.67500MHz (FM) 460KHz (AM) fcenter = 10.68125MHz (FM) 461KHz (AM) fcenter = 10.68750MHz (FM) 462KHz (AM) fcenter = 10.69375MHz (FM) 463KHz (AM) fcenter = 10.70000MHz (FM) 464KHz (AM) fcenter = 10.70625MHz (FM) 465KHz (AM) fcenter = 10.71250MHz (FM) 466KHz (AM) fcenter = 10.80000MHz (FM) 480KHz (AM) tsample = 20.48ms (FM) 128ms (AM) tsample = 10.24ms (FM) 64ms (AM) tsample = 5.12ms (FM) 32ms (AM) tsample = 2.568ms (FM) 16ms (AM) tsample = 1.28ms (FM) 8ms (AM) tsample = 640s (FM) 4ms (AM) tsample = 320s (FM) 2ms (AM) tsample = 160s (FM) 1ms (AM)
-
-
-
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SUBADDRESS 10: IF Counter Reference (LSB)
MSB D7 0 0 0 1 1 1 1 D6 0 0 0 1 1 1 1 D5 0 0 0 1 1 1 1 D4 0 0 0 1 1 1 1 D3 0 0 0 1 1 1 1 D2 0 0 0 1 1 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 0 0 1 0 1 FUNCTION LSB = 0 LSB = 1 LSB = 2 LSB = 252 LSB = 253 LSB = 254 LSB = 255
SUBADDRESS 11: IF Counter Reference (MSB) and IF Counter Mode select
MSB D7 D6 D5 0 0 0 1 1 1 D4 0 0 0 1 1 1 D3 0 0 0 1 1 1 D2 0 0 0 1 1 1 D1 0 0 1 0 1 1 LSB D0 0 1 0 1 0 1 FUNCTION MSB = 0 MSB = 256 MSB = 512 MSB = 15616 MSB = 15872 MSB = 16128 IF COUNTER MODE not valid IF counter FM mode (10.7KHz) IF counter AM mode (450KHz) not valid
-
-
0 0 1 0
0 1 0 0
Note: 1 fOSC/fTIM = LSB + MSB + 1
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SUBADDRESS 12: AM IF Amplifier gain and Ultra Narrow Band AGC Threshold, FM Smeter and AC test
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 test FM FS soft mute enable (FM mode) [bit shared with AM IF AMP Gain] 0 1 FS Soft mute disabled FS Soft mute enabled test AC mute (FM mode) [bit shared with AM IF AMP Gain] 0 1 test mode FM demod Vout is disconnected from users no test (std) AM IF AMP Gain (am mode) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not used 53.2dB 55.8dB 60.2dB 58.3dB 61.7dB 62.8dB 64.8dB AM UNAGC enable 1 0 Enable AM UNAGC Disable AM UNAGC AM Ultra Narrow Band AGC Threshold 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 74.4dBV @SG 78.8dBV @SG 80.0dBV @SG 80.7dBV @SG 119.5dBV @ IF2AMPOUT 53.2dBV @SG 77.1dBV @SG 78.5dBV @SG 79.4dBV @SG 42.7dBV @SG 65.8dBV @SG 77.6dBV @SG 78.5dBV @SG 32.6dBV @SG 113.5dBV @ IF2AMPOUT 55.0dBV @SG 73.3dBV @SG 77.6dBV @SG FUNCTION
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SUBADDRESS 13: Demodulator Fine Adjust and Noise Blanker, MP Qual test
MSB D7 D6 D5 D4 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 D3 0 0 1 0 0 1 D2 0 0 1 0 0 1 D1 0 0 1 0 0 1 LSB D0 0 1 1 0 1 1 FUNCTION Fm audio demodulator current adjust 0A 0.167A 2.51A 0A 0.167A 2.51A Demodulator Noise Blanker AM Smeter extension NB1&2 on (impvic&lontmas) old (10.7MHz) NB1 on (impvicmas) old (10.7MHz) NB2 on (implontmas0 new (450kHz) NB1&2 off new (450kHz) Multipath (ISS) test MP test OFF MP test ON (ISS quality detector MP input from #ACinL, ISS MP filter+rect output to Smeter test muxer if input 12 is selected
SUBADDRESS 14: Quality Detection Adjacent Channel
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ISS Filter for WB 0 1 ISS filter 30KHz OFF ISS filter 30KHz ON ISS Adjacent Channel filter configuration 0 1 AC highpass frequency 100KHz AC bandpass frequency 100KHz AC gain 0 1 32dB 38dB ISS Adjacent Channel threshold 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 -1 AC wide band threshold 0.25V AC wide band threshold 0.35V AC wide band threshold 0.45V AC wide band threshold 0.95V AC narrow band threshold 0V AC narrow band threshold 0.1V AC narrow band threshold 0.2V AC narrow band threshold 0.3V FUNCTION
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SUBADDRESS 15: Quality Detection Multipath and Smeter test
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ISS Multipath control enabling 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 Multipath control ON Multipath control OFF ISS Multipath filter center frequncy MP Bandpass frequency 19KHz MP Bandpass frequency 31KHz ISS Multipath filter input selector (test mode) Smeter unfilt test OFF Smeter unfilt test ON ISS Multipath threshold 0.5V 0.75V 1V 1.25V ISS mode Application mode 1 Application mode 2 ISS Multipath control mode MP control AC+ detection MP control the AC and AC+ detection FUNCTION
SUBADDRESS 16: Quality Detection Deviation
MSB D7 D6 D5 D4 D3 D2 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 D1 0 0 1 0 1 LSB D0 ISS deviation detector ime constant 0 1 0 0 1 charge current 34A; discharge current 6A charge current 32A; discharge current 8A charge current 30A; discharge curren10A charge current 26A; discharge current 14A charge current 20A; discharge current 20A ISS deviation detector thresholds DEV Threshold for ISS narrow-wide 30KHz DEV Threshold for ISS narrow-wide 45KHz DEV Threshold for ISS narrow-wide 60KHz DEV Threshold for ISS narrow-wide 75KHz DEV Threshold for ISS filter OFF ratio 1 DEV Threshold for ISS filter OFF ratio 1.3 DEV Threshold for ISS filter OFF ratio 1.4 DEV Threshold for ISS filter OFF ratio 1.5 not used AUX set int80 FUNCTION
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SUBADDRESS 17: Quality ISS Filter
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ISS automatic control fron AC detector 0 1 0 1 0 1 ON (AC drives ISSTC) OFF (AC has no influence on ISSTC) ISS manual control automatic control only manual force filter ON manual force BW 120KHz manual force BW 80KHz ISS time constant current: 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 shift from 450kHz discharge 1A 3A 5A 9A 15A ISS filter center frequency -20KHz -10KHz 0KHz 10KHz chrg mid 74A 72A 70A 66A 60A chrg narrow 124A 122A 120A 116A 110A FUNCTION FUNCTION FUNCTION FUNCTION
SUBADDRESS 18: PLL rest, 456KHz VCO adjust start, ISS MP Gain and SD out mode
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 D1 0 0 1 1 0 0 1 1 LSB D0 PLL TEST MODE 0 1 0 1 0 1 0 1 Automatic 456KHz VCO adjustment Waiting START ISS Multipath filter gain ISS MP Gain 2dB ISS MP Gain 13dB ISS MP Gain 16dB SD pin configuration ISS (IFC and FM SM Stop) IF Counter out FM Smeter Stop Logic 1 FUNCTION
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SUBADDRESS 19: 456KHz VCO adjustment (manual mode)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 FUNCTION Enable IFC (I2CBUS) OFF Enable IFC (I2CBUS) ON Enable 456KHz VCO adj procedure (I2CBUS) OFF Enable 456KHz VCO adj procedure (I2CBUS) ON VCO 456KHz frequency adjust (I2CBUS) minfreq
0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1
VCO 456KHz frequency adjust (I2CBUS) maxfreq Manual adjustment procedure (I2CBUS) Automatic adjustment procedure (State Machine)
SUBADDRESS 20: FM Stop Station and Soft Mute Threshold
MSB D7 D6 D5 D4 D3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 D2 0 0 1 1 D1 0 0 1 1 LSB D0 0 1 0 1 FUNCTION Soft Mute Threshold on Smeter 0mV 100mV 1.4V 1.5V FM Stop Station Threshold on Smeter 400mV 800mV 3.2V 3.6V
SUBADDRESS 21: Adjacent Channel Mute
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Adj Channel Mute Gain 10.4dB 11.4dB 12.4dB 13.4dB 14.4dB 15.4dB 16.4dB 17.4dB Adj Channel Mute Clamp 500mV 600mV 1.3V 1.9V 2V Adjacent Channel (ISS) test
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MSB 0 1 LSB FUNCTION AC test OFF AC test ON (ISS qualitydetector AC input from #ACinL, ISS AC filter+rect output to Smeter test muxer if input 12 is selected)
SUBADDRESS 22: FM Smeter Sider and AM Smeter Time Constant
MSB D7 D6 D5 D4 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 D3 0 0 1 1 D2 0 0 1 1 D1 0 0 1 1 LSB D0 0 1 0 1 FUNCTION FM Smeter Sider 0V 0.48V 1.45V 1.5V AM Smeter Filter TC (resistor value) 75K 50K 35K 24K 16K
SUBADDRESS 23: IFT Adjust
MSB D7 D6 D5 D4 D3 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 D2 0 0 1 1 D1 0 0 1 1 LSB D0 0 1 1 1 IFT1 Adjust 0pF 0.55pF 7.7pF 8.25pF IFT2 Adjust 75pF 50pF 22.4pF 24pF FUNCTION
SUBADDRESS 24: XTAL and FM IF AMP 2 Gain
MSB D7 D6 D5 D4 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 1 0 1 D2 0 0 0 1 0 1 0 D1 0 0 1 0 0 0 0 LSB D0 0 1 0 0 0 0 0 FUNCTION XTAL adjust Cload 0pF 0.625pF 1.25pF 2.5pF 5pF 10pF 10.4pF XTAL TEST) xtal clock clocksep (testing) FM IF Amp2 Gain
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MSB 0 0 1 1 LSB 0 1 0 1 6dB 8dB 10dB not used FUNCTION
SUBADDRESS 25: FM NAGC key and AM WAGC
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FM Narrow ACGC key IF input 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 36dB 42dB 48dB 54dB 60dB 66dB 72dB keying OFF AM WAGC starting point @ MIX1IN 0 1 0 1 0 1 0 1 0 1 88dBV 106dBV FUNCTION
SUBADDRESS 26: AM NAGC key and FM demod ref frequency test
MSB D7 D6 D5 D4 D3 D2 1 D1 1 LSB D0 0 test for FM demod ref freq divider (standard configuration) AM WAGC starting point @ MIX2IN 0 1 0 1 0 1 0 1 0 1 85dBV 103dBV FUNCTION
SUBADDRESS 27: ISS tests
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ISS test multiplexer (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 no test test MP thresholds test ACN thresholds test DW thresholds test D thresholds test ACW thresholds test ac FUNCTION
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MSB 0 1 1 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 test MDSCO test ISSout FUNCTION
SUBADDRESS 28: ISS tests
MSB D7 D6 D5 0 0 0 0 0 0 1 0 1 0 1 D4 0 0 0 0 0 1 0 D3 0 0 0 0 1 0 0 D2 0 0 0 1 0 0 0 D1 0 0 1 0 0 0 0 LSB D0 0 1 0 0 0 0 0 FUNCTION ISS test multiplexer (2) no test test dev+ test dev+ test ref dev test dem Vout test ISS in test ISSC ik Enble ISS test in test in ISS disable test in ISS enable ISS test clock test ISS clock disable test ISS clock enable
SUBADDRESS 29: Tuner and Smeter tests
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 SMETER test multiplexer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 test off test AMAGC1W test AMAGC1N test AMAGC1UN test FM Smute Threshold test FMSMStop test AMIF2Amp test AMSDDAC test FMKAGC test FMACMDisable test FMDemodAdjON test FMDemodAdjONMute test FMACMuteRct test FSISSONThreshold test FSISSON test ISSInput Smeter OUT ACD enable test Smete IN FUNCTION
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MSB 0 1 LSB FUNCTION Smeter filter force enable test TMODE1OUT (byte 27/28)
SUBADDRESS 30: Adjacent channel mute
MSB D7 D6 D5 D4 D3 0 0 1 1 1 0 1 0 1 D2 0 0 0 1 1 D1 0 0 0 1 1 LSB D0 0 1 0 0 1 FUNCTION Adjacent channel mute threshold 0mV 28.7mV 229.3mV 401.3mV 430mV Adjacent channel mute filter configuration AdjChannel Mute HighPass filter 1 AdjChannel Mute BandPass filter 1 AdjChannel Mute HighPass filter 2 AdjChannel Mute BandPass filter 2 Adjacent channel mute disable @ low FS threshold 1V threshold 1.33V threshold 1.66V threshold 2V
0 0 1 1
0 1 0 1
SUBADDRESS 31: Adjacent channel and Multipath gain, weak field ISS threshold
MSB D7 D6 D5 D4 D3 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D2 0 0 1 0 0 1 1 D1 0 0 1 0 0 1 1 LSB D0 0 1 1 0 1 0 1 FUNCTION Weak field ISS activation threshold -450mV -385.7mV -0mV +0mV 64.28mV 385.7mV 450mV Turner Quality Multipath gain 0 (OFF) dB -4dB 0dB 4dB Turner Quality Adjacent channel gain (OFF) -4dB 0dB 4dB
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6.3 ADDRESS ORGANIZATION (STEREODECODER AND AUDIOPROCESSOR SECTION)
MSB Subaddr.
0 1 2 3 4 5 6 7 8 NB time not used bass DC mode treble center freq bass Q factor volume steps volume steps volume steps volume steps bass center frequency NB peak dis NB on VHCL Quality del. coeff. force mono not used auto zero status soft mute time
LSB D6 D5
in gain volume steps treble steps bass steps
Function
Source selector, in gain, peaker coupling Volume Treble Bass Speaker attenuator Left Front Speaker attenuator Right Front Speaker attenuator Left Read Speaker attenuator Right Rear
D7
spkr coupl
D4
D3
D2
D1
source selector
D0
I2C soft Soft mute, soft mute time, Bass, mute off Noise blanker time Stereo decoder mute, st dec instd mute gain, mono, NB PEAK disch curr., disable pilot thresh, deemph. Noise Blanker high cut High cut, multipath influence on not used Fieldstrength control Noise rectifier disch. resistor, Multipath del. bandpass gain, multipath internal influence, reflection gain Roll-off compensation, level gain
9 10 11 12
deemph.
pilot thr.
std in gain low threshold max high out NB field strength threshold
overdev. adj mpath. infl. mpath. infl.
noise contr.thresh. VHCH NB field strength gain
13
mpath. det. Reflect. Gain roll-off compens. AP test ON 400K ON
mpath. charge
mpath.int. infl
mpath.det gain
noise rect.disch, R
14 15 16 17 18
level gain test signal selection
roll-off compensation Itest SC OFF quality noise gain mid steps VSBL
SID test TEST BYTE ON mpath test AMHCC, Quality noise gain, test Mid
AM high cut control corner frequency mid Qfactor mid center frequency not used
Stereo blend
SUBADDRESS
MSB D7 testcon D6 azhold D5 autoincr D4 D3 D2 subaddress D1 LSB D0
READ MODE
MSB S7 S6 S5 S4 S3 STEREO S2 SMON S1 LSB S0
ADDRESS
MSB S7 1 S6 0 S5 0 S4 0 S3 1 S2 1 S1 0 LSB S0 R/W
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6.4 SUBADDRESS ORGANIZATION (STEREODECODER AND AUDIOPROCESSOR SECTION) SUBADDRESS 0: Source selector, in-gain, Speaker coupling
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Source Selector 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Quasi-differential input 1 Quasi-differential input 2 not used (mute) Turner input (AM mode) Turner input (FM mode) not used (mute) not used (mute) not used (mute) In-Gain 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0dB 1dB 14dB 15dB Speaker Coupling 0 1 AC (external) DC (internal) FUNCTION
Subaddress 1,4,5,6,7: Volume Spkr atten. LF, RF, LR, RR
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Volume steps 1 1 0 0 0 0 0 0 X 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 X 1 0 0 0 1 0 1 1 X 1 0 0 0 1 0 1 1 X 1 0 0 0 1 0 1 1 X 1 1 0 1 1 0 0 1 X 15dB 1dB 0dB -1dB -15dB -15dB -78dB -79dB mute FUNCTION
all other combinations not allowed
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Subaddress 2: Treble
MSB D7 D6 D5 D4 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 D3 0 0 1 1 1 1 0 0 D2 0 0 1 1 1 1 0 0 D1 0 0 1 1 1 1 0 0 LSB D0 Treble filter steps 0 1 0 1 1 0 1 0 -15dB -14dB -1dB 0dB 0dB 1dB -14dB -15dB Treble filter center frequency 10.0kHz 12.5kHz 15kHz 17.5kHz FUNCTION
Subaddress 3: Bass
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Bass filter steps 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 0 -15dB -14dB -1dB 0dB 0dB 1dB -14dB -15dB Bass filter Q-factor 0 0 1 1 0 1 0 1 1.00 1.25 1.50 2 (makes cent. freq. = 150Hz when programmed to 100Hz) Bass filter DC mode 0 1 off on FUNCTION
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Subaddress 4: Speaker attenuator Left Front
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Volume steps 1 1 0 0 0 0 0 0 X 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 X 1 0 0 0 1 0 1 1 X 1 0 0 0 1 0 1 1 X 1 0 0 0 1 0 1 1 X 1 1 0 1 1 0 0 1 X 15dB 1dB 0dB -1dB -15dB -15dB -78dB -79dB mute FUNCTION
all other combinations not allowed
Subaddress 8: Soft mute, Bass, Noise blanker time
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Soft mute activation control 0 1 I2C bus Audio Processor mute ON (independently of pin Audio Mute) I2C bus Audio Processor mute OFF (pin Audio Mute controls muting: pin=0 mute ON, pin=1 mute OFF) Soft mute transition time = 0.48ms Soft mute transition time = 0.96ms Soft mute transition time = 20.2ms Soft mute transition time = 40.4ms Base filter center frequency 0 0 1 1 1 0 1 0 1 1 60Hz 70Hz 80Hz 100Hz (if bass DC mode OFF) 150Hz (if bass DC mode ON) Noise Blanker time 0 0 1 1 0 1 0 1 38s 25.5s 32s 22s FUNCTION
0 0 1 1
0 1 0 1
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Subaddress 9: Stereo decoder mute, st. dec. in-gain, mono, NB PEAK disch, Curr., pilot thresh, deemph
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 FUNCTION Stereo Decoder Mute high-ohmic mute, pilot hold, multipath time constant short ENABLED (mute set by pin RDS mute LOW) high-ohmic mute, pilot hold, multipath time constant short DISABLED (regardless of pin RDS mute) Stereo Decoder In-gain 0dB 2.5dB 4dB 5.5dB Auto Zero Status disabled enabled; trans. 0 1 performs Autozero sequence Force MONO ON OFF (automatic MONO/STEREO switch) Noise PEAK discharge current low High Pilot Threshold low High Demphasis 50s 75s
1 1 0 0 0 1 0 1 0 1 0 1 0 1
1 0 1 0
Subaddress 10: Noise blanker
MSB D7 D6 D5 D4 D3 D2 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 LSB D0 0 1 1 FUNCTION Low threshold 65mV 60mV 30mV Noise controlled threshold 320mV 260mV 200mV 140mV Noise Blanker operation OFF ON Overdeviation adjustment 2.8V 2.0V 1.2V OFF
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Subaddress 11: High cut, multipath influence
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION High cut operation OFF ON Max high cut 2dB 5db 7dB 10dB VHCH 42% REF 5V 50% REF 5V 58% REF 5V 66% REF 5V VHCL 16.7% VHCH 22.2% VHCH 27.8% VHCH 33.3% VHCH Strong Multipath influence on PEAK 18K OFF ON (18K discharge if VMPOUT <2.5V)
Subaddress 12: Fieldstrength control
MSB D7 D6 D5 D4 D3 D2 D1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 LSB D0 Noise Blanker Fieldstrength threshold 0 0 1 1 max Noise Blanker Fieldstrength Gain 2.3V 1.8V 1.3V OFF Quality detector coefficient a a = 0.7 a = 0.85 a = 1.0 a = 1.15 Multipath influence on PEAK discharge OFF ON min FUNCTION
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Subaddress 13: Noise rectifierdisch, resistor, Multipath del. bandpass gain, multipath internal influence, reflection gain
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 FUNCTION Noise Rectifier Discharge Resistor R = infinite R = 56K R = 33K R = 18K Multipath Detector Bandpass Gain 6dB 12dB 16dB 18dB Multipath Detector Internal Influence ON OFF Multipath Detector Change Current 0.5A 1A Multipath Detector Reflection Gain Gain = 7.6dB Gain = 4.6dB Gain = 0dB disabled
Subaddress 14: Roll-off compensation, level gain
MSB D7 0 0 0
-
D6
D5
D4
D3
D2 0 0 0
-
D1 0 0 1
-
LSB D0 0 1 0
-
FUNCTION Roll-off compensation not allowed 7.2% 9.4% 13.7% 20.2% not allowed 19.6% 21.5% 25.3% 31.0% Level gain 0dB 0.66dB 1.33dB 10dB
0
-
1
-
0
-
0
-
0 1 1 1
-
1 0 0 0
-
1 0 0 1
-
1 0 1 0
-
1
-
1
-
0
-
0
-
1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 1
1
1
1
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Subaddress 15: TEST BYTE
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Stereo Decoder test signals enabling test signal disabled test signal enabled (if S6=1) on ACinR Stereo Decoder test signals selection VHCCH LEVELINTERN PILOT VCOCON (VCO tuning violtage) PIL_VTH HOLDN NB_VTH F228 VHCCL VSBL state machine enable ifc state machine set456 PEAK state machine check REF 5V SBPWM Test SC filter Fast test enabled (2-phase 200KHz clock) Test disabled (4-phase 200KHz clock) 400 KHz VCO OFF OFF ON Audio processor test enabling Test disabled Test enabled (if S6=1)
Subaddress 16: Multipath test, AMHCC
D7 D6 D5 D4 D3 D2 D1 D0 Multipath test enable 0 1 0 0 1 1 0 0
-
Multipath Detector test input disabled Multipath Detector test input enabled Quality detector noise gain 15dB 12dB 9dB 6dB AM High-cut control corner frequency
0 1 0 1
0 0
-
0 0
-
0 0
-
0 1
-
1 1
1 1
1 1
1 1
0 1
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Subaddress 17: Mid
MSB D7 D6 D5 D4 0 0
-
D3 0 0
-
D2 0 0
-
D1 0 0
-
LSB D0 0 1
-
FUNCTION Mid Filter steps -15dB -14dB -1db 0dB 0dB 1dB 14dB 15dB Mid Filter center frequency 500Hz 1.0KHz 1.5KHz 2.0KHz Mid Filter Q factor 1.0 2.0
0 0 1 1
-
1 1 1 1
-
1 1 1 1
-
1 1 1 1
-
0 1 1 0
-
1 1 0 0 1 1 0
1
0 0
0 0
0 0
1 0
0 1 0 1
Subaddress 18: Stereo blend
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 1 D1 0 0 1 1 0 0 1 1 1 LSB D0 0 1 0 1 0 1 0 0 1 FUNCTION VSBL VSBL at 29% REF 5V VSBL at 33% REF 5V VSBL at 38% REF 5V VSBL at 42% REF 5V VSBL at 46% REF 5V VSBL at 29% REF 5V VSBL at 50% REF 5V VSBL at 54% REF 5V VSBL at 58% REF 5V
-
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Figure 22. TQFP80 Mechanical Data & Package Dimensions
mm MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.22 0.09 16.00 14.00 12.35 0.65 16.00 14.00 12.35 0.60 1.00 0.75 0.018 1.40 0.32 TYP. MAX. 1.60 0.15 1.45 0.38 0.20 0.002 0.053 0.009 0.003 0.630 0.551 0.295 0.0256 0.630 0.551 0.486 0.024 0.0393 3.5(min.), 7(max.) 0.030 0.055 0.013 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.015 0.008
DIM.
OUTLINE AND MECHANICAL DATA
TQFP80 (14x14x1.40mm)
D D1 D3
A A2
A1
60 61 41 40
0.10mm .004 Seating Plane
e
E3 B
E1
E
PIN 1 IDENTIFICATION
Gage plane 0.25mm
80 1 20
21
K
TQFP80L
C L L1
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Table 29. Revision History
Date June 2004 Revision 1 First Issue Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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